As technology gravitates towards denser and faster integrated circuits, efficient utilization of chip area becomes inceasingly significant. In the case of amplifier technology, where fast sensing of a voltage differential is required, the demands for speed and reliability necessitate more innovative aproaches to circuit design. High-speed sensing and latching of data is particularly desirable in memories and microprocessors, however standard sense amplifiers are often too slow for use in these environments. Designs for faster sense amplifiers generally require additional chip area.
The reduction of both device size and device count, in circuit implementation of fast sense amplifiers, is required for efficient utilization of chip area. In the prior art are sense amplifiers implemented using a single differential portion. Single-ended amplifier designs may reduce device count, but they require additional circuitry to generate symmetric latched outputs. Generally, single-ended sense amplifiers are too slow for use in high-performance microprocessors. Consequently, sense amplifiers were commonly implemented with a double-ended amplifier design, which provides symmetric outputs. These double-ended amplifiers use two differential portions, each comprised generally of a current mirror, and an inverting amplifier. Sense amplifiers using double-ended designs, for level-shifting and symmetrical sensing of logic `0` and `1`, may provide fast sensing, however they also require more devices. As a rule, the chip area required for double-ended amplifiers is larger, and they require more DC current for their operation. Furthermore, the use of a latch in series with the amplifier takes up additional chip area.